Functional simulation refers to the process of verifying the correctness of the created logic before the design is realized in the design.
The previous layout simulation is called functional simulation, including pre-synthesis simulation and post-synthesis simulation. The pre-synthesis simulation is mainly aimed at the design based on the principle block diagram; The comprehensive simulation is suitable for both schematic design and design based on HDL language.
2. Time series simulation (post-simulation)
Timing simulation uses the delay information of modules and lines given by devices after layout and wiring to actually evaluate the behavior of the circuit in the worst case. Simulators used for time series simulation are the same as those used for functional simulation, and the required processes and incentives are the same; The only difference is that the worst-case layout delay based on the actual layout design is included in the design of time series simulation loaded into the simulator, while in the waveform diagram of simulation results, the signal after time series simulation is loaded with delay, while the functional simulation is not.